1. Field of the Invention
This invention relates to electronic assembly technology and more specifically to solder bump interconnections for mounting chips with copper I/O pads to an interconnection substrate.
2. Description of the Related Art
As chips continue to decrease in size, pure copper circuits have been found to have undeniable advantages that traditional aluminum interconnects cannot match. Copper wires conduct electricity with about 40 percent less resistance than aluminum. That translates into a speedup of as much as 15 percent in microprocessors that contain copper wires. Furthermore, copper wires are also far less vulnerable than those made of aluminum to electromigration, the movement of individual atoms through a wire, caused by high electric currents, which creates voids and ultimately breaks the wires. Most important, the widths of copper wires can be squeezed down to the 0.2-micron range from the current 0.35-micron widthsxe2x80x94a reduction far more difficult for aluminum. Conventional aluminum alloys cannot conduct electricity well enough, or withstand the higher current densities needed to make these circuits switch faster when wires with very small dimensions is used. Gradually chips with copper interconnects will substitute for chips with traditional aluminum interconnects.
Moreover, as electronic devices have become smaller and thinner, the velocity and the complexity of IC chips has increased. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the u sage of advanced pack ages such as chip scale packages (CSP) and flip chips. Both greatly reduce the amount of board real estate required when compared to the alternative ball grid array (BGA) and quad flat pack (QFP). Typically, a CSP is 20 percent larger than the die itself, while the flip chip has been described as the ultimate package precisely because it has no package. The bare die itself is attached to the substrate by means of solder bumps directly attache to the die.
Flip-chip bumping technology typically comprises (a) forming an under bump metallurgy (UBM) on bonding pads of the chip, and (b) forming metal bumps on the UBM. Typically, UBM consists of three metal layers, including: (a) adhesion layer (formed of Al or Cr) for purposes of providing a good adhesion to Al pad and passivation layer; (b) barrier layer (formed of NiV or TiW) for preventing contact pads on the chip and the bump electrode from reacting with each other to generate an intermetallic compound (which is harmful to the reliability of chip); and (c) wetting layer (formed of Ni, Cu, Mo or Pt) wherein that kind of metals provide a higher wetting power to solder thereby allowing for proper wetting of solder during solder-reflow process. Typically, the metal bump is made of conductive material (such as metal high melting point solder alloys, low melting point solder alloys, gold, nickel or copper), depending on the characteristics needed in the to-be-formed flip-chip.
FIG. 1 is a cross sectional view of a conventional semiconductor having a bump electrode. An aluminum contact pad 110 is formed on a substrate 120 of a semiconductor integrated circuit. A passivation film 130, serving as an insulation film, is formed on the entire surface of the substrate 120. A passivation opening section which is formed at a predetermined position, is formed to expose the aluminum contact pad 110. The semiconductor device 100 has a UBM 140 consisting of three metal layers, including: (a) aluminum layer 140a used as the adhesion layer; (b) nickel-vanadium layer 140b used as the barrier layer; and (c) copper layer 140c used as the wetting layer.
However, the UBM 140 is not applicable to chips with copper contact pads because of poor aluminum-to-copper adhesion. Therefore, the semiconductor industry has developed a semiconductor device 200 (see FIG. 2) wherein the UBM 240 consists of two metal layers, including: (a) titanium layer 240a used as the adhesion layer and the barrier layer; and (b) copper layer 240b used as the wetting layer. Although the titanium layer has a good adhesion to both of the passivation layer 130 and the copper contact pad 210, it has a disadvantage of poor electric conductivity as compared to a copper layer.
The present invention therefore seeks to provide an under bump metallurgy which overcomes, or at least reduces the above-mentioned problems of the prior art.
It is a primary object of the present invention to provide an under bump metallurgy (UBM) adapted for chip with copper contact pads wherein the UBM is capable of providing a better electrical performance.
It is another object of the present invention, by integrating the UBM of the present invention with I/O distribution, to provide a semiconductor device having a structure that permits rearrangement of contact pads and provides a better electrical performance.
The UBM of the present invention is applied to a chip with copper contact pads in order to form a semiconductor device having bump electrodes. Typically, the chip comprises a substrate and at least one copper contact pad on the substrate. A passivation layer is formed over the substrate and has an opening positioned over the al least one copper contact pad. The UBM includes a titanium layer, a first copper layer, a nickel-vanadium layer and a second copper layer. The titanium layer forms a closed-loop surrounding the opening of the dielectric layer. The first copper layer is formed over the titanium layer and the opening of the dielectric layer such that the first copper layer directly contacts the copper contact pad. The nickel-vanadium layer is formed on the first copper layer and the second copper layer is formed on the nickel-vanadium layer. A metal bump is provided on the UBM over the copper contact pad thereby forming a bump electrode. Consequently, the semiconductor device of the present invention can be directly mounted to a interconnection substrate by means of bump electrodes directly attached thereon.
The UBM of the present invention is characterized by using the titanium layer with a closed-loop shape as the adhesion layer to significantly increase the adhesion between the UBM and the passivation layer, and using the first copper layer, which is directly contacted with the copper contact pad, to provide a better electrical performance.
The present invention further provides a semiconductor device having a structure that permits rearrangement of contact pads. The semiconductor device comprises a substrate having a copper contact pad formed thereon; a first dielectric layer formed over the substrate, the first dielectric layer having a first opening positioned over the copper contact pad; a multi-layered lead having a first end portion connected to the copper contact pad through the first opening and a second end portion extending on the first dielectric layer; a second dielectric layer formed over the multi-layered lead and the first dielectric layer, the second dielectric layer having a blind-via formed corresponding to the second end portion of the multi-layered lead; a conductive pad formed over the blind-via; and a metal bump provided on the conductive pad. The multi-layered lead includes a first titanium layer on the first dielectric layer, a copper layer on the first titanium layer and a second titanium layer on the copper layer wherein the first titanium layer has a second opening corresponding to the first opening and the copper layer directly contacts the copper contact pad through the second opening and the first opening.